赵晓田 Xiaotian Zhao

In this work, we propose DARE, which extracts hidden connections between macros and standard cells and incorporates a series of algorithms to enrich dataflow awareness, integrating them into placement constraints for improved macro placement. To further optimize placement results, we introduce two fine-tuning steps: (1) congestion optimization by taking macro area into consideration, and (2) flipping decisions to determine the optimal macro orientation based on the extracted dataflow informatio

In this paper, we propose the tight integration of versatile MPQ inference units supporting INT2-INT8 and INT16 precisions, which feature a hierarchical multiplier architecture, into a RISC-V processor pipeline through micro-architecture and Instruction Set Architecture (ISA) co-design.

In this study, we identify the necessity of macro-cell connection awareness for high-quality macro placement and propose a novel methodology to extract all “hidden” relationships efficiently among macros and cell clusters.

In this work, we propose a novel MPQ search algorithmthat obtains an optimal scheme by “sampling” layer-wise sensi-tivity with respect to a newly proposed metric that incorporatesboth accuracy and proxy of hardware cost. To further efficientlydeploy post-training MPQ on edge chips, we propose to tightly inte-grate the quantized inference units as part of the processor pipelinethrough micro-architecture and Instruction Set Architecture (ISA)co-design.